1. Field of the Invention
This invention generally relates to filters and duplexers, and more particularly, to filter and a duplexer mounted on a laminated package or a laminated substrate.
2. Description of the Related Art
In recent years, mobile terminal devices and personal digital assistances have been widely used with the developments in the mobile communication system. The mobile terminal devices utilize high frequency ranges of 800 MHz to 2.0 GHz. Accordingly, there have been proposed high-frequency filters provided to the devices for use in mobile communication and antenna duplexers having the high-frequency filters.
Elastic wave filters, for example, are used as the high-frequency filters. The elastic wave filters include surface acoustic wave (SAW) filters that are small-sized, lightweight, and excellent in shape factor and film bulk acoustic Resonator (FBAR) filters that are excellent in high-frequency characteristics and can be downsized. There are demands for higher performance, downsizing, and cost reduction of the high-frequency filters and duplexers. Accordingly, there have been proposed filters in which a filter chip is mounted on the laminated package having a laminated portion or the laminated substrate and duplexers in which the filter is included.
Japanese Patent Application Publication No. 2004-336181 (hereinafter, referred to as Document 4) discloses the filter and the duplexer having a filter chip mounted on a laminated package or laminated substrate having a laminated portion in which a ceramic substrate and the like are laminated. There are other conventional techniques that downsize the filter and duplexer. A line pattern for phase matching is provided in two layers, as disclosed in Japanese Patent Application Publication No. 8-18393 (hereinafter, referred to as Document 1). Multiple line patterns for phase matching are provided, as disclosed in Japanese Patent Application Publication No. 10-75153 (hereinafter, referred to as Document 2). Multiple line patterns for phase matching are also provided in the circumference of the chip, as disclosed in Japanese Patent Application Publication No. 2001-339273 (hereinafter, referred to as Document 3). The line pattern for phase matching is provided in multiple layers, as disclosed in Document 4.
Document 1 describes that the line pattern for phase matching is provided in two layers. However, the line pattern for phase matching is provided only on the side of an antenna terminal, and there is no description on the line for phase matching provided on a transmitting terminal or receiving terminal. This is because the technique disclosed in Document 1 is applied to the duplexer for 800 MHz band, which has less influence of parasite impedance of the package than that of the duplexer for 2 GHz band. For this reason, there exists a problem that cannot be solved, if the filter matching is not successful in the high-frequency duplexer of 2 GHz band.
Document 2 describes that the multiple line patterns for phase matching are provided. However, the line for phase matching provided on the side of the transmitting terminal or on the side of the receiving terminal is not provided in two layers. This also causes a problem that cannot be solved, if the filter is not matched in the high-frequency duplexer of 2 GHz band especially.
Document 3 describes that the multiple line patterns for phase matching are provided in the circumference of the chip. Accordingly, the package size becomes larger and cannot be reduced.
Document 4 describes that the line pattern for phase matching is provided in multiple layers. However, there is no description on the direction of current flowing through the line pattern for phase matching. Accordingly, there exist problems that a large self-inductance cannot be created in a small space and the impedance matching cannot be improved by the capacitance between the signal line and the ground.